Monthly Archives: February 2012

vmm example — atomic gen

`timescale 1ns/1ns //interface interface bus(input clk); logic [7:0] addr; logic [31:0] data; clocking cb @(posedge clk); default input #1ns output #1ns; output addr; output data; endclocking modport master (clocking cb); endinterface //transaction class bus_tran extends vmm_data; rand logic [7:0] addr; … Continue reading

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