使用IUS自带的shm保存仿真波形

在verilog文件中实现:

module test();
reg clk

initial begin
clk = 0;
forever #1 clk = ~clk;
end

initial begin
$shm_open(“waves.shm”);
$shm_probe(“AC”);
#1000 $finish;
end
endmodule

###################################################################
在tcl脚本中实现:
database -shm -default waves
probe -shm top -depth all -all
run
exit

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