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vmm example — atomic gen

`timescale 1ns/1ns
//interface
interface bus(input clk);
logic [7:0] addr;
logic [31:0] data;

clocking cb @(posedge clk);
default input #1ns output #1ns;
output addr;
output data;
endclocking

modport master (clocking cb);

endinterface

//transaction
class bus_tran extends vmm_data;

rand logic [7:0] addr;
rand logic [31:0] data;

static vmm_log log = new(“bus tran log”, “bus tran log0″);

function new();
super.new(this.log);
endfunction

virtual function string psdisplay(string prefix=””);
super.psdisplay(prefix);
$sformat(psdisplay, “%s time: %t “, psdisplay, $time);
$sformat(psdisplay, “%s addr: %h “, psdisplay, this.addr);
$sformat(psdisplay, “%s data: %h “, psdisplay, this.data);
endfunction: psdisplay

virtual function vmm_data copy(vmm_data to = null);
bus_tran cpy;

if(to == null)
cpy = new();
else begin
if(!$cast(cpy, to)) begin
`vmm_fatal(this.log, “Error to cast to to cpy”);
cpy = null;
return cpy;
end
end

super.copy_data(cpy);
cpy.addr = this.addr;
cpy.data = this.data;

return cpy;

endfunction: copy

endclass

//channel
`vmm_channel(bus_tran)
//generator
`vmm_atomic_gen(bus_tran, “bus_tran_atomic_gen”)

//driver
class bus_driver extends vmm_xactor;

virtual bus.master bus_if;
bus_tran_channel bus_ch;

function new(
virtual bus.master bus_if,
bus_tran_channel bus_ch
);
super.new(“bus_driver”, “bus_driver1”);
this.bus_if = bus_if;
this.bus_ch = bus_ch;
endfunction

task main();
bus_tran bus_tr;
bus_tran bus_tr_cpy;

super.main();

forever begin
bus_ch.get(bus_tr);
$cast(bus_tr_cpy, bus_tr.copy());
bus_tr_cpy.display();
@(bus_if.cb);
bus_if.cb.addr <= bus_tr_cpy.addr;
bus_if.cb.data <= bus_tr_cpy.data;
end
endtask

endclass

//bus_env
class bus_env extends vmm_env;

virtual bus.master bus_if;
bus_tran_atomic_gen bus_gen;
bus_driver bus_drv;
bus_tran_channel bus_ch;

function new(virtual bus.master bus_if);
super.new(“bus_env”);
this.bus_if = bus_if;
endfunction

function void build();
super.build();
bus_ch = new(“bus channel”, “bus chan0”);
bus_gen = new(“bus_gen”, 0, bus_ch);
bus_drv = new(bus_if, bus_ch);
endfunction

task start();
super.start();
fork
bus_gen.start_xactor();
bus_drv.start_xactor();
join_none
endtask

task wait_for_end();
super.wait_for_end;
this.bus_gen.notify.wait_for(bus_tran_atomic_gen::DONE);
#1000;
endtask

endclass

///////////////////////////////////////////////////////////
//test — use default
///////////////////////////////////////////////////////////
program test(bus.master bus_if);

bus_env e = new(bus_if);

initial begin
e.build();
e.bus_gen.stop_after_n_insts = 10;
e.run();
end

endprogram

//top

module top();

reg clk;

initial begin
clk = 0;
forever #10 clk = ~clk;
end

initial begin
$vcdpluson();
end

bus bus0(clk);

test test1(
bus0.master
);

dut u_dut(
.addr(bus0.addr),
.data(bus0.data)
);

endmodule

//dut

module dut(
addr,
data
);
input [7:0] addr;
input [31:0] data;
endmodule

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一些免费的systemverilog的学习网站

http://testbench.in/

http://www.asic-world.com/

http://www.asicguru.com/

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各大EDA公司的支持网站

 
 
 
 
 
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在IUS中通过仿真命令参数传递变量

################################################################################
#make.csh
################################################################################
#!/bin/tcsh -f
#
#

set NOVAS_INST_DIR = /disks/depot3/novas/verdi200907

setenv LD_LIBRARY_PATH ${NOVAS_INST_DIR}/share/PLI/nc_latest/LINUX/nc_shared:${LD_LIBRARY_PATH}

if($1 =~ “”) then
irun -sv test.sv
else
irun -sv +FSDB_EN=1 -access +rwc test.sv
endif

################################################################################
#test.sv
################################################################################
module test();
reg clk;
integer en;

initial begin
clk = 0;
forever #1 clk = ~clk;
end

initial begin
if($value$plusargs(“FSDB_EN=%d”, en)) begin
$display(“value was %d”, en);
$fsdbDumpfile(“./wave.fsdb”);
$fsdbDumpvars(0, test);
$fsdbDumpon();
end
else begin
$display(“not need to dump wave”);
end
#1000 $finish();
end
endmodule

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使用IUS自带的shm保存仿真波形

在verilog文件中实现:

module test();
reg clk

initial begin
clk = 0;
forever #1 clk = ~clk;
end

initial begin
$shm_open(“waves.shm”);
$shm_probe(“AC”);
#1000 $finish;
end
endmodule

###################################################################
在tcl脚本中实现:
database -shm -default waves
probe -shm top -depth all -all
run
exit

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在IUS使用tcl进行交互

####################################################################
#make.csh
####################################################################

#!/bin/tcsh -f
#
#

set NOVAS_INST_DIR = /disks/depot3/novas/verdi200907
if($1 =~ “64”) then
set PLATFORM = LINUX64
else
set PLATFORM = LINUX
endif
setenv LD_LIBRARY_PATH ${NOVAS_INST_DIR}/share/PLI/nc_latest/${PLATFORM}/nc_shared:${LD_LIBRARY_PATH}

if($1 =~ “64”) then
irun -sv -64bit test.sv -input input.tcl
else
irun -sv -access +rwc test.sv -input input.tcl
endif

####################################################################
#input.tcl
####################################################################
#call fsdbDumpfile wave.fsdb
#call fsdbDumpvars 0 test
#call fsdbDumpon
run
exit

####################################################################
#test.sv
####################################################################
module add(a, b, c);
input a, b;
output c;

assign c = a + b;
endmodule

module test();
reg clk;

initial begin
clk = 0;
forever #1 clk = ~clk;
end

initial begin
#1000 $finish();
end

reg a, b;
wire c;

initial begin
a = 0;
b = 0;
#1 a = 0;
b = 1;
#1 a = 1;
b = 0;
#1 a = 1;
b = 1;
#1 a = 0;
b = 0;
end

add u_add (
.a(a),
.b(b),
.c(c)
);

endmodule

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